A 17.8 MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS (bibtex)

by P. Brown, M. O'Shaughnessy, C. Rozell, J. Romberg and M. Flynn

Abstract:

Transceiver bandwidth limits the resolution of ultra- low-power pulse radar systems. Compressed sensing techniques improve resolution but existing efforts require heavy computation. This work proposes a neural-network based compressed sensing radar processor architecture that improves resolution by 6x while remaining computationally efficient. Fabricated in 16nm FinFET CMOS, the processor simultaneously achieves more than 8x throughput and 18x efficiency over the state-of-the-art.

Reference:

A 17.8 MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOSP. Brown, M. O'Shaughnessy, C. Rozell, J. Romberg and M. Flynn. March 2020.

Bibtex Entry:

@CONFERENCE{brown.20,
     author = 	 {Brown, P. and O'Shaughnessy, M. and Rozell, C. and Romberg, J. and Flynn, M.},
     title = 	 {A 17.8 {MS/s} Neural-Network Compressed Sensing Radar Processor in 16nm {FinFET} {CMOS}},
     booktitle =	 {IEEE Custom Integrated Circuits Conference (CICC)},
     year =	 2020,
  	 month = mar,
  address = {Boston, MA},
  abstract = {Transceiver bandwidth limits the resolution of ultra- low-power pulse radar systems. Compressed sensing techniques improve resolution but existing efforts require heavy computation. This work proposes a neural-network based compressed sensing radar processor architecture that improves resolution by 6x while remaining computationally efficient. Fabricated in 16nm FinFET CMOS, the processor simultaneously achieves more than 8x throughput and 18x efficiency over the state-of-the-art.}
  }